1. Field of the Invention
The present invention relates to a nonvolatile semiconductor device and a method of fabricating the same, and more particularly, to a nonvolatile semiconductor device for preventing electric field accumulation and having improved electrical properties, and a method of fabricating the same.
2. Description of the Related Art
Scaling (shrinking) is a continuing process in the manufacture and design of nonvolatile semiconductor devices, wherein device feature sizes continue to decrease to increase switching speed, to achieve high performance, and to reduce power consumption while maintaining a high drive capacity.
One scaling technology that has been proposed for increasing the density of a semiconductor device is a multi-gate transistor having a fin-shaped silicon body formed on a silicon-on-insulator (SOI) wafer and a gate formed on the surface of the fin-shaped silicon body (e.g., Fu-Liang Yang et al., “35 nm CMOS FinFETs”, Symposium on VLSI Technology Digest of Technical Papers, pp. 104-105, 2002; and B. S. Doyle et al., “High Performance Fully-Depleted Tri-gate CMOS Transistors”, IEEE Electron Device Letters, Vol. 24, No. 4, April, 2003, pp. 263-365).
When a nonvolatile semiconductor device is made of a multi-gate transistor, a three-dimensional channel is used in the scaling technology. Further, the sub-threshold characteristic and the current control capacity can be improved without increasing the gate length by employing a complete depletion SOI structure. In addition, a short channel effect (SCE), in which the electric potential of the channel region is affected by the drain voltage, can be suppressed. In particular, a tri-gate structure using channels formed on three planes of a semiconductor body is beneficial in terms of a large design error allowance with respect to the width and height of the semiconductor body.
However, the electric field is not uniform in all three planes of the semiconductor body in the tri-gate structure, but it is concentrated at the corners of the semiconductor body. The semiconductor body has a rectangular cross section produced by dry etching a semiconductor layer. The electric field is concentrated at the corners of this rectangular cross section and the threshold voltage at the corners is low. Accordingly, the channel forms faster at the corners than other portions so that the switching characteristic is degraded there. Further, when an oxide layer, a polysilicon layer, a nitride layer, and others are formed on the semiconductor body, the respective layers are formed on {100} and {110} crystal planes at different formation speeds, resulting in serious non-uniformity of the characteristics of the nonvolatile semiconductor device.
Meanwhile, when the semiconductor body having channels formed on a plurality of planes is fabricated by dry etching, it is highly probable that charge carriers are created within an insulating layer formed on the semiconductor body by damage due to plasma generated during the dry etching. Further, surface roughness of the semiconductor body may deteriorate, resulting in a reduction in carrier mobility.